Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Yusuke KannoHiroyuki MizunoYoshihiko YasuKenji HiroseYasuhisa ShimazakiTadashi HoshiYujiro MiyairiToshifumi IshiiTetsuya YamadaTakahiro IritaToshihiro HattoriKazumasa YanagisawaNaohiko IriePublished in: ISSCC (2006)
Keyphrases
- low power
- power distribution
- high speed
- single chip
- power consumption
- cmos technology
- gate array
- low cost
- nm technology
- high power
- power reduction
- transmission line
- vlsi architecture
- digital signal processing
- power management
- logic circuits
- mixed signal
- vlsi circuits
- power dissipation
- energy efficiency
- low power consumption
- power saving
- image sensor
- energy dissipation
- real time
- instruction set
- application specific
- parallel processing
- multiscale
- image processing