Low Power Reversible Parallel Binary Adder/Subtractor
H. G. RangarajuU. VenugopalK. N. MuralidharaK. B. RajaPublished in: CoRR (2010)
Keyphrases
- low power
- logic circuits
- high speed
- power consumption
- low cost
- power dissipation
- single chip
- high power
- wireless transmission
- vlsi circuits
- vlsi architecture
- digital signal processing
- low power consumption
- image sensor
- parallel processing
- massively parallel
- data flow
- power reduction
- image processing
- hardware and software
- multi threaded
- cmos technology
- general purpose
- video sequences
- delay insensitive
- real time