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A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process.
Dong-Hyun Yoon
Kwang-Hyun Baek
Tony Tae-Hyoung Kim
Published in:
ESSCIRC (2022)
Keyphrases
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power consumption
clock gating
dielectric constant
phase locked loop
high speed
low power
power reduction
multimedia
digital libraries
low frequency
digital media
small size
text to speech
frequency distribution
clock frequency