Login / Signup

A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor.

Pierre BisiauxCaroline Lelandais-PerraultAnthony KolarPhilippe BénabèsFilipe Vinci dos Santos
Published in: SBCCI (2016)
Keyphrases
  • cmos image sensor
  • single chip
  • parallel processing
  • dynamic range
  • analog to digital converter
  • solid state
  • processing capabilities
  • low power
  • high speed
  • sigma delta