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A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption.
Sotir Ouzounov
Engel Roza
Johannes A. (Hans) Hegt
Gerard van der Weide
Arthur H. M. van Roermund
Published in:
IEEE J. Solid State Circuits (2005)
Keyphrases
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power consumption
low power
low voltage
power management
energy efficiency
cmos technology
power saving
control method
battery life
energy saving
power reduction
battery powered
power dissipation
transfer function
nm technology
real time
low cost
analog to digital converter
single chip
data center
data streams