Comparative Experiment of SPIN and SMT in Model Checking of Embedded Assembly Program.
Satoshi YamaneKosuke UemuraPublished in: GCCE (2020)
Keyphrases
- model checking
- temporal logic
- model checker
- automated verification
- formal verification
- partial order reduction
- temporal properties
- formal specification
- finite state
- transition systems
- reachability analysis
- symbolic model checking
- computation tree logic
- bounded model checking
- reactive systems
- finite state machines
- epistemic logic
- timed automata
- concurrent systems
- process algebra
- verification method
- dynamic analysis
- pspace complete
- formal methods
- static analysis