Design of the Convolution Layer Using SoC FPGA and Evaluation of Latency Using a Camera Signal.
Ryoki KamesakaYukinobu HoshinoPublished in: SCIS/ISIS (2020)
Keyphrases
- real time
- signal processing
- design process
- low cost
- high frequency
- camera calibration
- embedded systems
- camera parameters
- single chip
- hardware design
- multiple cameras
- gate array
- abstraction layer
- formative evaluation
- fir filters
- fast fourier transform
- hand held
- hardware implementation
- surveillance system
- high speed
- response time