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1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance.
Hyeonsik Kim
Seonkyung Kim
Jintae Kim
Published in:
A-SSCC (2021)
Keyphrases
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high speed
power consumption
clock gating
low power
power dissipation
cmos technology
hd video
nm technology
wide dynamic range
power supply
real time
parameter estimation
sar images
synthetic aperture radar
dynamic range
analog to digital converter