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1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance.

Hyeonsik KimSeonkyung KimJintae Kim
Published in: A-SSCC (2021)
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