Design of a 32-bit Datapath for a Reduced Instruction Set Computers (RISC) Implementation using the DE0-nano FPGA.
Jose B. LazaroMaribelle D. PabianiaLewmorc James S. BitangcorJohn Carlo Benedict De TorresJoseph Marxlen A. DumapitJayvee N. MapotePublished in: ICCAE (2024)
Keyphrases
- instruction set
- instruction set architecture
- computer architecture
- hardware architecture
- embedded systems
- dedicated hardware
- floating point
- application specific
- fpga device
- computer systems
- ibm power processor
- field programmable gate array
- real time
- hardware implementation
- low power consumption
- low cost
- xilinx virtex
- memory subsystem
- signal processing
- level parallelism
- memory space
- single chip
- object oriented
- information systems
- artificial intelligence