SDCNN: An Efficient Sparse Deconvolutional Neural Network Accelerator on FPGA.
Jung-Woo ChangKeon-Woo KangSuk-Ju KangPublished in: DATE (2019)
Keyphrases
- neural network
- field programmable gate array
- high speed
- pattern recognition
- artificial neural networks
- hardware implementation
- high dimensional
- fuzzy logic
- compressed sensing
- parallel computing
- parallel implementation
- compressive sensing
- real time image processing
- signal processing
- fpga implementation
- sparse data
- multi layer perceptron
- systolic array
- computing systems
- network architecture
- associative memory
- prediction model
- self organizing maps
- sparse representation
- low cost
- genetic algorithm