Channel complexity analysis for reconfigurable VLSI/WSI processor arrays.
Phill K. RheeJung H. KimPublished in: ASAP (1990)
Keyphrases
- complexity analysis
- single chip
- high speed
- systolic array
- low cost
- digital signal
- gate array
- multi channel
- theoretical analysis
- lower bound
- reconfigurable architecture
- chip design
- focal plane
- parallel processing
- functional units
- low power
- general purpose
- first order logic
- hardware implementation
- signal processing
- parallel architecture
- central processing unit
- vlsi circuits
- vlsi design
- computational complexity
- content addressable memory
- real time
- computation intensive
- data flow
- machine learning
- vlsi implementation
- evolutionary algorithm
- heterogeneous computing
- knowledge representation