A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques.
Sahel AbdiniaMohammad YavariPublished in: ICECS (2009)
Keyphrases
- low power
- high speed
- vlsi architecture
- power consumption
- low cost
- mixed signal
- cmos technology
- single chip
- real time
- high power
- data flow
- digital signal processing
- nm technology
- low power consumption
- vlsi circuits
- image sensor
- parallel architecture
- logic circuits
- signal processor
- design considerations
- general purpose
- vlsi implementation
- power reduction
- frame rate
- cmos image sensor