Power Estimation of CMOS Circuits by Neural Network Macromodel.
Wei QiangYang CaoYuan-yuan YanXun GaoPublished in: ISNN (2) (2006)
Keyphrases
- neural network
- power consumption
- power dissipation
- chip design
- analog vlsi
- high speed
- circuit design
- delay insensitive
- low power
- cmos technology
- power reduction
- analog circuits
- vlsi circuits
- artificial neural networks
- pattern recognition
- genetic algorithm
- recurrent neural networks
- power management
- low voltage
- focal plane
- logic circuits
- estimation accuracy
- accurate estimation
- low cost
- bp neural network
- prediction model
- neural network model
- real time
- floating gate
- electronic circuits
- network architecture
- estimation algorithm
- multilayer perceptron
- infrared
- fuzzy logic
- image sequences