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Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding.

Marcelo TosiniMartín VázquezLucas Leiva
Published in: J. Supercomput. (2024)
Keyphrases
  • efficient implementation
  • hardware implementation
  • efficient processing
  • highly parallel
  • image processing
  • active set
  • general purpose