Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes.

Yang Sun Guohui Wang Joseph R. Cavallaro

Published in: ISCAS (2011)

Keyphrases

multi layer
ldpc codes
low density parity check
decoding algorithm
vlsi architecture
error correction
channel coding
message passing
vlsi implementation
low complexity
low power
neural network
noise model
belief propagation
non binary
image transmission
rate allocation
computer simulation
graphical models
multiscale