Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
Hua WangMiguel MirandaAntonis PapanikolaouFrancky CatthoorWim DehaenePublished in: IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
- low power
- vlsi architecture
- cmos technology
- power consumption
- single chip
- low cost
- ultra low power
- high speed
- low power consumption
- digital signal processing
- power reduction
- embedded systems
- logic circuits
- gate array
- signal processor
- vlsi circuits
- power dissipation
- efficient implementation
- vlsi implementation
- mixed signal
- design process
- low voltage
- design considerations
- design methodology
- low complexity
- circuit design
- finite element