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A HiperLAN II frame processor implementation.

E. P. VasilakopoulouGeorge D. PapadopoulosGeorge E. Karastergios
Published in: Wirel. Commun. Mob. Comput. (2003)
Keyphrases
  • cell broadband engine architecture
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  • parallel processing
  • real time
  • neural network
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  • high speed
  • hardware implementation
  • single chip