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Optimized ASIC/FPGA Design Flow for Energy Efficient Network Nodes.
Hans Sahm
Matthias Sauppe
Erik Markert
Thomas Horn
Ulrich Heinkel
Klaus-Holger Otto
Published in:
Bell Labs Tech. J. (2013)
Keyphrases
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energy efficient
hardware architecture
single chip
wireless sensor networks
sensor networks
energy consumption
building blocks
hardware implementation
software engineering
design process
routing protocol
energy efficiency
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