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A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.
Kyungsu Kang
Sangho Park
Jong-Bae Lee
Luca Benini
Giovanni De Micheli
Published in:
DATE (2016)
Keyphrases
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ibm power processor
high speed
low cost
single chip
power dissipation
multithreading
real time
computing systems
memory subsystem
instruction set
cache conscious