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Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.

Fady AbouzeidAudrey BienfaitKaya Can AkyelAnis FekiSylvain ClercLorenzo CiampoliniFabien GinerRobin WilsonPhilippe Roche
Published in: IEEE J. Solid State Circuits (2014)
Keyphrases
  • cmos technology
  • nm technology
  • power consumption
  • low power
  • knowledge based systems
  • power dissipation
  • user interface
  • real time
  • neural network
  • high speed
  • engineering design
  • single chip
  • power reduction