Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.
Ari KulmalaErno SalminenTimo D. HämäläinenPublished in: DDECS (2007)
Keyphrases
- level parallelism
- memory hierarchy
- multimedia
- instruction set
- hardware architecture
- hardware implementation
- signal processing
- real time
- multithreading
- software implementation
- power reduction
- fpga implementation
- associative memory
- mpeg standard
- hardware design
- low cost
- parallel architecture
- multi core processors
- processing elements
- parallel processing
- rate distortion
- image compression
- single chip
- floating point
- computational power
- dedicated hardware
- bit rate
- parallel hardware