Low-power inter-core communication through cache partitioning in embedded multiprocessors.
Chenjie YuXiangrong ZhouPeter PetrovPublished in: SBCCI (2009)
Keyphrases
- low power
- embedded processors
- single chip
- high speed
- low cost
- power consumption
- multithreading
- shared memory multiprocessors
- high power
- embedded systems
- parallel implementation
- wireless transmission
- logic circuits
- vlsi circuits
- low power consumption
- vlsi architecture
- gate array
- image sensor
- parallel computing
- shared memory
- digital signal processing
- resource constrained
- communication networks
- real time
- mixed signal
- communication systems
- delay insensitive
- message passing
- parallel processing
- wireless sensor networks