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Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
Rostislav (Reuven) Dobkin
Michael Peleg
Ran Ginosar
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
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vlsi architecture
low latency
vlsi implementation
low power
low complexity
real time
data streams
computational complexity
high speed
data management
frequency domain
stream processing