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A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.

Mingqiang HuangYucen LiuQuan ChengShuxin YangKai LiJunyi LuoZhengke YangQiufeng LiHao YuChanghai Man
Published in: FPGA (2022)
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