Tutorial: How to Use Model Checking to Analyze Circuits at the Transistor Level.
Michael RaitzaSteffen MärckerPublished in: CODES+ISSS (2023)
Keyphrases
- model checking
- temporal logic
- high speed
- asynchronous circuits
- formal verification
- temporal properties
- automated verification
- finite state
- symbolic model checking
- partial order reduction
- finite state machines
- formal specification
- epistemic logic
- verification method
- model checker
- timed automata
- reachability analysis
- linear temporal logic
- reactive systems
- formal methods
- process algebra
- pspace complete
- planning domains
- knowledge representation
- artificial intelligence
- power dissipation
- binary decision diagrams
- low power
- deterministic finite automaton