Parallel Symbol Timing Recovery Using FPGA for 600 Msps QPSK.
Di HuangZhijie WangJun WangZiyao LiuPublished in: ChinaCom (1) (2017)
Keyphrases
- parallel hardware
- systolic array
- low cost
- high speed
- parallel processing
- parallel implementation
- real time
- parallel architecture
- neural network
- parallel programming
- parallel computation
- field programmable gate array
- massively parallel
- hardware implementation
- signal processing
- parallel computing
- real time image processing
- high data rate
- genetic algorithm
- verilog hdl