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Inverter-Based 1.82 mW 68.6~ dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques.
Sebastian Zeller
Christian Muenker
Robert Weigel
Thomas Ussmueller
Published in:
IEEE J. Solid State Circuits (2014)
Keyphrases
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power consumption
nm technology
cmos technology
low power
single chip
power dissipation
power management
high speed
metal oxide semiconductor
power reduction
low cost
chip design
circuit design
medical images
low voltage
reactive power
design methodology
computer aided
three dimensional
analog to digital converter