A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.
Carlo CondoPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2022)
Keyphrases
- heterogeneous computing
- lookup table
- pattern matching
- error rate
- scheduling problem
- management system
- associative memory
- scheduling algorithm
- real time
- response time
- fpga implementation
- resource utilization
- wireless broadcast
- scheduling strategy
- inverse halftoning
- error bounds
- resource allocation
- parallel architecture
- low complexity
- high speed
- motion estimation