Hardware Implementation of an Efficient Correlator for Interleaved Complementary Sets of Sequences.
María del Carmen PérezJesús UreñaÁlvaro HernándezCarlos De MarzianiAna JiménezWilliam P. MarnanePublished in: J. Univers. Comput. Sci. (2007)
Keyphrases
- hardware implementation
- efficient implementation
- signal processing
- hardware design
- fpga implementation
- hardware architecture
- dedicated hardware
- software implementation
- hidden markov models
- pipeline architecture
- sequential patterns
- image binarization
- field programmable gate array
- image processing algorithms
- memory management
- fpga technology
- real time
- processing elements
- information systems
- fpga device