A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC.
D. MeganathanAmrith SukumaranM. M. Dinesh BabuS. MoorthiR. DeepalakshmiPublished in: Microelectron. J. (2009)
Keyphrases
- low power
- single chip
- analog to digital converter
- low cost
- power consumption
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- mixed signal
- power dissipation
- image sensor
- high power
- ultra low power
- wireless transmission
- digital signal processing
- cmos technology
- nm technology
- vlsi implementation
- power reduction
- vlsi circuits
- design process
- circuit design
- hardware and software
- embedded systems
- wireless networks
- real time