A multi-processor NoC-based architecture for real-time image/video enhancement.

Sergio Saponara Luca Fanucci Esa Petri

Published in: J. Real Time Image Process. (2013)

Keyphrases

multi processor
real time
program execution
single processor
shared memory
network on chip
multi core processors
input image
image retrieval
low cost
image classification
image processing
resource management
packet switched