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3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS.
Mukesh Kumar Srivastav
Rimjhim
Roshan Mishra
Anuj Grover
Kedar Janardan Dhori
Harsh Rawat
Published in:
ISCAS (2022)
Keyphrases
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cmos technology
silicon on insulator
low cost
high speed
low power
data flow
circuit design
power supply
low voltage
delay insensitive
bit rate
hierarchical structure
power consumption
bi directional
analog vlsi
vlsi circuits
neural network