Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing.
Tse-Wei ChenMakoto IkedaPublished in: COOL Chips (2012)
Keyphrases
- high throughput
- low power
- hardware architecture
- signal processing
- hardware implementation
- high speed
- power consumption
- digital signal processing
- low cost
- microarray
- biological data
- processing elements
- signal processor
- genome wide
- data acquisition
- low power consumption
- systems biology
- field programmable gate array
- microarray gene
- protein protein interactions
- image processing
- proteomic data
- parallel processing
- cmos technology
- power dissipation
- gene expression data
- mass spectrometry data
- image sensor
- mass spectrometry
- gene expression
- real time
- parallel computing
- general purpose
- parallel algorithm
- distributed memory
- logic circuits
- software engineering
- cluster analysis
- automated image analysis
- wireless sensor networks
- ultra low power
- shared memory