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A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication
Rourab Paul
Sangeet Saha
J. K. M. Sadique Uz Zaman
Suman Das
Amlan Chakrabarti
Ranjan Ghosh
Published in:
CoRR (2012)
Keyphrases
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efficient implementation
hardware implementation
high speed
data acquisition
active set
efficient processing
fpga device
hardware design
highly parallel
np hard
low cost
dedicated hardware
hardware architectures