A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOS.
Eric P. PepinJohn P. UehlinDaniel MichelettiSteve I. PerlmutterJacques Christophe RudellPublished in: ESSCIRC (2016)
Keyphrases
- high voltage
- cmos technology
- silicon on insulator
- operating conditions
- nm technology
- power consumption
- low power
- network architecture
- neural network
- back end
- metal oxide semiconductor
- partial discharge
- normal operation
- high speed
- low cost
- affine transformation
- biologically plausible
- analog vlsi
- electric field
- feature space
- data mining
- data mining techniques
- circuit design
- image sensor
- self organizing maps