A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder.
Yuanzhi ZhangChao LuPublished in: IEEE Trans. Circuits Syst. Video Technol. (2019)
Keyphrases
- highly parallel
- bit rate
- hardware architecture
- coding efficiency
- intra coding
- rate distortion
- intra prediction
- video coding standard
- video coding
- hardware implementation
- efficient implementation
- macroblock
- video codec
- coding method
- visual quality
- bitstream
- subband
- motion vectors
- image quality
- parallel architectures
- rate distortion optimization
- inter frame
- video quality
- compression efficiency
- low bit rate
- field programmable gate array
- rate control
- mode decision
- computing systems
- distributed video coding
- computational complexity
- video compression
- single pass
- motion compensation
- motion compensated
- inter view
- scalable video coding
- graphics processing units
- transform domain
- general purpose
- computer vision
- bit allocation
- high performance computing
- error resilience
- image coding
- video encoder
- motion estimation