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Examining the consequences of high-level synthesis optimizations on power side-channel.

Lu ZhangWei HuArmaiti ArdeshirichamYu TaiJeremy BlackstoneDejun MuRyan Kastner
Published in: DATE (2018)
Keyphrases
  • high level synthesis
  • power consumption
  • parallel architecture
  • design space exploration
  • np hard
  • smart card
  • countermeasures
  • secret key