A low-power, area-efficient digital filter for decimation and interpolation.

Brian P. Brandt Bruce A. Wooley

Published in: IEEE J. Solid State Circuits (1994)

Keyphrases

low power
low cost
power consumption
high speed
mixed signal
vlsi circuits
single chip
deblocking filter
high power
digital signal processing
wireless transmission
multi channel
logic circuits
delay insensitive