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Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic.

Massimo AliotoLuca PancioniSantina RocchiValerio Vignoli
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2007)
Keyphrases
  • positive feedback
  • power consumption
  • neural network
  • learning algorithm
  • noisy data
  • flip flops
  • logic programming
  • noise level
  • power dissipation