Hardware Implementation of Fano Decoder for Polarization-Adjusted Convolutional (PAC) Codes.
Amir MozammelPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2022)
Keyphrases
- hardware implementation
- decoding algorithm
- ldpc codes
- fpga implementation
- low density parity check
- signal processing
- reed solomon
- efficient implementation
- parity check
- hardware design
- dedicated hardware
- field programmable gate array
- parallel architecture
- error control
- error correction
- non binary
- belief propagation
- software implementation
- noise model
- joint source channel
- pipeline architecture
- hardware architecture
- image processing algorithms
- image binarization
- fpga technology
- image processing
- neural network
- decision feedback
- real time
- computer vision