A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm.
Arash AbadianMojtaba LotfizadNasser Erfani MajdMohammad Bagher Ghaznavi GhoushchiH. MirzaiePublished in: ICECS (2010)
Keyphrases
- low complexity
- low power
- cmos technology
- vlsi architecture
- mixed signal
- nm technology
- power consumption
- high speed
- low cost
- motion estimation
- phase locked loop
- power reduction
- low density parity check
- low voltage
- distributed video coding
- bit plane
- computational complexity
- parallel processing
- multiple description coding
- image sensor