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A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm.
Arash Abadian
Mojtaba Lotfizad
Nasser Erfani Majd
Mohammad Bagher Ghaznavi Ghoushchi
H. Mirzaie
Published in:
ICECS (2010)
Keyphrases
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low complexity
low power
cmos technology
vlsi architecture
mixed signal
nm technology
power consumption
high speed
low cost
motion estimation
phase locked loop
power reduction
low density parity check
low voltage
distributed video coding
bit plane
computational complexity
parallel processing
multiple description coding
image sensor