Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA.
Sophie BouchouxEl-Bay BourennaneJohel MitéranMichel PaindavoinePublished in: ISVLSI (2004)
Keyphrases
- fpga implementation
- hardware implementation
- field programmable gate array
- decoding process
- low cost
- image coding
- efficient implementation
- hardware architectures
- dedicated hardware
- signal processing
- image processing
- hardware architecture
- software implementation
- fpga technology
- fpga device
- hardware design
- compression algorithm
- image compression