A Hybrid Approach for Parallel Transistor-Level Full-Chip Circuit Simulation.
Heidi K. ThornquistSivasankaran RajamanickamPublished in: VECPAR (2014)
Keyphrases
- high speed
- circuit design
- power dissipation
- analog vlsi
- chip design
- low power
- power consumption
- higher level
- cmos technology
- parallel processing
- simulation model
- queuing systems
- real time
- level parallelism
- parallel execution
- single chip
- integrated circuit
- printed circuit boards
- evolvable hardware
- mathematical analysis
- massively parallel
- low cost