Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.
Saurabh TewariAnshul KumarKolin PaulPublished in: ISVLSI (2020)
Keyphrases
- memory access
- data access
- main memory
- instruction set
- memory management
- high speed
- ibm power processor
- direct memory access
- shared memory
- external memory
- operating system
- high volume
- access patterns
- processing units
- single chip
- computing systems
- data storage
- memory efficient
- databases
- memory bandwidth
- data objects
- database management systems
- general purpose