Investigating cache energy and latency break-even points in high performance processors.
Kaveh Jokar DerisAmirali BaniasadiPublished in: MEDEA@PACT (2006)
Keyphrases
- embedded processors
- prefetching
- single chip
- parallel implementation
- data points
- hit ratio
- energy consumption
- feature points
- memory hierarchy
- low latency
- point sets
- distributed memory
- parallel computers
- access patterns
- parallel algorithm
- load balance
- replacement policy
- energy efficient
- multiprocessor systems
- heterogeneous computing
- memory subsystem
- compute intensive
- cache misses
- web caching
- coarse grained
- response time