Low power-area designs of 1bit full adder in cadence virtuoso platform.
Karthik Reddy GPublished in: CoRR (2013)
Keyphrases
- low power
- nm technology
- logic circuits
- power dissipation
- power consumption
- low cost
- high speed
- single chip
- high power
- real time
- low power consumption
- wireless transmission
- gate array
- vlsi circuits
- digital signal processing
- bit parallel
- cmos technology
- vlsi architecture
- ultra low power
- data flow
- power saving
- power reduction
- general purpose