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A flexible linear array oriented VLSI processor for continuous speech recognition.
Jun-ichi Takahashi
Takashi Kimura
Shigetatsu Hamaguchi
Naotaka Omiya
Published in:
ICASSP (1987)
Keyphrases
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continuous speech recognition
linear array
processing elements
single chip
high speed
gate array
parallel processing
random access
real time
signal processing
hardware architecture
high end
chip design
parallel processors
massively parallel
hardware implementation
associative memory
low cost