Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor.
Ubaid AhmadAmir AminMin LiSofie PollinLiesbet Van der PerreFrancky CatthoorPublished in: ICC (2011)
Keyphrases
- multi processor
- parallel processing
- single processor
- distributed memory
- computer architecture
- multi core processors
- multiprocessor systems
- shared memory
- high speed
- parallel architectures
- parallel architecture
- high end
- level parallelism
- data parallelism
- parallel processors
- instruction set
- parallel implementation
- parallel computing
- lattice structure
- map reduce
- processing elements
- cell processor
- multithreading
- discrete cosine transform
- massively parallel
- motion estimation
- graphics processing units
- multicore processors
- systolic array
- multi core architecture
- shared memory multiprocessors