An FPGA-based accelerator for rapid simulation of SC decoding of polar codes.

Johannes Wüthrich Alexios Balatsoukas-Stimming Andreas Burg

Published in: ICECS (2015)

Keyphrases

decoding algorithm
error correcting
error correction
rotation invariant
parity check
reed solomon codes
simulation model
joint source channel
ldpc codes
analytical model
simulation environment
parallel implementation
mathematical model
image processing
error control
reed solomon
low cost