A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators.
Eunyoung LeeTaeyoung HanDonguk SeoGicheol ShinJaerok KimSeonho KimSoyoun JeongJohnny RheJaehyun ParkJong Hwan KoYoonmyung LeePublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2021)